This invention relates to the architecture of a particular type of digital logic circuit called a programmable multiplexer.
In general, practically all digital logic circuits are packaged on semiconductor chips in accordance with the particular function that they perform. See, for example, The TTL Data Book for Design Engineers, 2nd Edition, Texas Instruments, Section 1 page 9 wherein several logic circuit chips are listed according to their function, and in particular note the "data selector-multiplexer" chips since they relate directly to the subject of this invention.
Each data selector-multiplexer chip there listed contains one or more fixed multiplexer circuit which is herein defined as a circuit having a plurality of data inputs, a plurality of control inputs, and an output. In operation, control signals are applied to the control inputs, and in response the fixed multiplexer circuit selectively passes a signal from one of the data inputs to the output. In other words, the data inputs are multiplexed to the output in response to the control signals in a fixed predetermined fashion.
Typically, several fixed multiplexer circuits are fabricated on a single chip. See, for example, the Texas Instruments chips 54LS253 and 74LS253 in Section 7, page 369 of the above-cited reference. These chips contain two such circuits, each of which has four data inputs and one output; and the data inputs on both of those circuits are selected by control signals that are common to both circuits.
One significant limitation, however, to these 54LS253 and 74LS253 chips and other similar prior art chips containing several fixed multiplexer circuits is that they are too inflexible. More specifically, the data inputs which the several fixed multiplexer circuits select in response to the control signals cannot be picked in any desired combination. Instead, the data inputs which pass to the outputs in response to the control signals are fixed. Typically, in response to control signals encoded as a "binary one", all of the fixed multiplexer circuits select their "first" data input; in response to control signals encoded as a "binary two", all of the fixed multiplexer circuits select their "second" data input; etc.
To overcome this problem, a "programmable multiplexer" chip has been recently introduced into the market by a company called Monolithic Memories. This programmable multiplexer chip has a part number 29693, and its block diagram is illustrated in FIG. 1.
As there illustrated, this programmable multiplexer is comprised of four fixed multiplexer circuits 11-14 and a corresponding number of fusible link arrays 15-18. In operation, input signals i.sub.0 -i.sub.9 are received on the chip by buffers 20; and their outputs are sent to the fusible link arrays. Outputs from the fusible link arrays 15-18 are then sent to the fixed multiplexer circuits 11-14 respectively.
Circuits 11-14 pass their inputs to their output in a fixed predetermined fashion in response to a common set of control signals S.sub.0 -S.sub.2. But this 29693 chip is much more flexible than the aforementioned Texas Instruments 54LS253 and 74LS253 chips because the fuse arrays enable the input signals i.sub.0 -i.sub.8 to be passed to the fixed multiplexer circuits 11-14 in any desired combination.
Suppose, for example, that it is desired to pass inputs i.sub.7, i.sub.2, i.sub.8, and i.sub.0 through the fixed multiplexer circuits 11, 12, 13 and 14 respectively in response to S.sub.0, S.sub.1, S.sub.2 signals of 001. Assuming that a 001 code selects the first input on each of the fixed multiplexer circuits 11, 12, 13, and 14, then the above result is achieved by merely blowing the appropriate fuses in arrays 15, 16, 17, and 18 such that input i.sub.7 is sent to the first input of fixed multiplexer circuit 11, input i.sub.2 is sent to fixed multiplexer circuit 12, etc.
However, despite the above-described desirable feature of the FIG. 1 programmable multiplexer chip, that chip also has several very significant drawbacks. And these drawbacks, along with the features and advantages of the present invention, are described in detail in the following Detailed Description in conjunction with FIGS. 2-5.
Accordingly, a primary object of the present invention is to provide an improved programmable multiplexer chip as described in conjunction with FIGS. 2-5.